MPC8xx Clock Configuration Spreadsheet Utility

CONNOTECH Experts-conseils inc.

PPCMB/850 Product Family Documentation

System Engineering Support Document

March 2003 (revised July 2003 and February 2004)

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SPLL (System Phase Lock Loop)

// External Oscillator Frequency    Hz          H/W design
// Crystal (EXTAL/XTAL) Frequency   Hz          H/W design

// MODCK[1-2]                                   H/W design
// HRCW(EBDF)                                   H/W design
// MPC850 speed                     Hz          H/W design

// OSCCLK                            10000000 Hz          EXTCLK_freq
// PLPRCR(MF) at reset                      4 
// GCLK2 at reset                    50000000 Hz          
// CLKOUT at reset                   50000000 Hz          

// PLPRCR(MF) during operation                  S/W design

// Operation (1) vs Power-up (0)                spreadsheet alternative

// Applicable PLPRCR(MF)                    4 

// VCOOUT                            50000000 Hz                      

// SCCR(DFSYNC)                                 S/W design
// SYNCCLK                           50000000 Hz                      

// SCCR(DFBRG)                                  S/W design
// BRGCLK                            50000000 Hz          

// SCCR(DFNL)                                   S/W design
// SCCR(DFNH)                                   S/W design
// PLPRCR(CSRC)                                 S/W operation
// GCLK2                             50000000 Hz          

// SCCR(EBDF)                                   S/W design
// CLKOUT                            50000000 Hz          

// High frequency GCLK2              50000000 Hz          
// High frequency CLKOUT             50000000 Hz          

// Low frequency GCLK2               25000000 Hz          
// Low frequency CLKOUT              25000000 Hz

Timebase and Decrementer

// SCCR(TBS)                                    S/W design

// Clock source                      50000000 Hz          GCLK2

// TMBCLK prescaler                        16 

// TMBCLK resolution                    0.320 micro-s     
// DECrementer max. period           1374.390 s           
// Timebase range                  187053.455 years

clock_t Type Made From the Timebase Counter

// clock_t significant bits         bits        S/W design
// clock_t minimum rollover period  days        S/W design
// clock_t minimum rollover count 135000000000 
// clock_t rollover bits                   37 bits        
// clock_t resolution                 0.01024 ms          
// clock_t actual rollover period      0.5090 days        
// CLOCKS_PER_SEC                    97656.25 
//                                Low power behavior: mode LOW disrupts, mode SLEEP stops

Timer Tick Using the Decrementer

// Period, nominal                  ms          S/W design
// Period in TMBCLK units               31250 
// Period, actual                       10.00 ms          
// Period rounding error                0.000 %           
//                                Low power behavior: mode LOW disrupts, mode SLEEP stops

PIT and RTC Clocks

// SCCR(RTSEL)                                  S/W design
// SCCR(RTDIV)                                  S/W design

// Real-Time Clock source            10000000 Hz          EXTCLK
// Real-Time Clock divisor                512 

// PITRCLK                              19531 Hz          
// PIT and RTC lsb resolution          0.0512 ms          

// RTCSC(38K)                                   S/W design
// RTC "one second" period           0.419430 s           
// RTC range                           57.084 years

clock_t Type Made From the RTC Counter

// clock_t significant bits         bits        S/W design
// clock_t minimum rollover period  days        S/W design
// clock_t minimum rollover count   843750000 
// clock_t rollover bits                   32 bits        
// clock_t resolution                 0.05120 ms          
// clock_t actual rollover period      2.5452 days        
// CLOCKS_PER_SEC                    19531.25 
//                                Low power behavior: mode DEEP SLEEP stops

Timer Tick Using the PIT Counter

// PIT period, nominal              ms          S/W design
// PITC(PITC)                             195 
// PIT period, actual                    9.98 ms          
// PIT period rounding error            0.160 %           
//                                Low power behavior: mode DEEP SLEEP stops

Software Watchdog

// Input clock, operating            50000000 Hz          

// Input clock, reset                50000000 Hz          
// Watchdog period, reset               2.684 s           

// SYPCR(SWP)                               1 
// SYPCR(SWTC)                           5005 

// Watchdog period, nominal         ms          S/W design
// Watchdog period, margin          ms          S/W design
// Watchdog period, actual            205.005 ms          

// Watchdog period, low clock mode    410.010 ms          

// C--- intermediate values ---   

// Watchdog period, total               0.205 s           
// SYPCR(SWTC), assuming SWP=0       10250000 
// SYPCR(SWTC), assuming SWP=1           5005

Bus Monitor Timing

// BMT clock source                   6250000 Hz          

// BMT period, nominal              nanno-s     S/W design
// SYPCR(BMT)                              63 
// BMT period, actual                   10080 nanno-s     

// BMT period, low clock mode           20160 nanno-s

Baud Rate Generators

// BRGCLK                            50000000 Hz          
// CLK2                             Hz          H/W design
// CLK4                             Hz          H/W design

Asynchronous Baud Rates Clocking

        |   BRGCLK      |    CLK2       |    CLK4       |
        |DIV16          |DIV16          |DIV16          |
  Speed |     CD     %  |     CD     %  |     CD     %  |
    600 | 1  3250.15 | 0  1030.16 | 0 33320.01 |
   1200 | 0 26030.01 | 0   510.16 | 0 16660.02 |
   2400 | 0 13010.01 | 0   250.16 | 0  8320.04 |
   4800 | 0  6500.01 | 0   120.16 | 0  4160.08 |
   9600 | 0  3250.15 | 0    66.99 | 0  2070.16 |
  14400 | 0  2160.01 | 0    38.51 | 0  1380.08 |
  19200 | 0  1620.15 | 0    28.51 | 0  1030.16 |
  28800 | 0  1080.45 | 0    18.51 | 0   680.64 |
  38400 | 0   800.47 | 0    118.62 | 0   510.16 |
  57600 | 0   530.47 | 0    08.51 | 0   340.79 |
  76800 | 0   400.76 | 0    018.62 | 0   250.16 |
 115200 | 0   260.47 | 0    045.75 | 0   162.12 |
 230400 | 0   133.12 | 0    072.87 | 0    83.55 |
 460800 | 0    63.12 | 0    086.44 | 0    38.51 |

High Speed DPLL Clocking

// Minimum                          Hz          S/W design
// Maximum                          Hz          S/W design
// GSMR_L(xDCR)                                 S/W design
// DPLL ratio                              32 

             |  BRGCLK   |   CLK2    |   CLK4    |
             |DIV16      |DIV16      |DIV16      |
             |       CD  |       CD  |       CD  |
             |  0    31  |  0     0  |  0    19  |
Actual freq. |  48828 Hz |  31250 Hz |  50000 Hz |

SPI Clocking

// Minimum                          Hz          H/W design
// Maximum                          Hz          H/W design
// Forced DIV16                                 S/W design

// SPMODE(DIV16)                            0 
// SPMODE(PM)                               3 
// Actual freq.                       3125000 Hz

I2C Clocking

// Minimum                          Hz          H/W design
// Maximum                          Hz          H/W design
// I2MOD(FLT)                                   H/W design

  I2MOD(PDIV) I2BRG  Actual frequency
          0     0       260417 ERROR I2BRG too small
          1     0       520833 ERROR I2BRG too small
          2     1       781250 ERROR I2BRG too small
          3     4       892857 Hz

UPM Refresh Timing

// BRGCLK                            50000000 Hz          


// BR0(MS)                          GPCM        H/W design
// BR1(MS)                          UPMA        H/W design
// BR2(MS)                          UPMB        H/W design
// BR3(MS)                          GPCM        H/W design
// BR4(MS)                          GPCM        H/W design
// BR5(MS)                          GPCM        H/W design
// BR6(MS)                          GPCM        H/W design
// BR7(MS)                          GPCM        H/W design

//                                       UPMA        UPMB        GPCM 
// CS0                                      0           0           1 
// CS1                                      1           0           0 
// CS2                                      0           1           0 
// CS3                                      0           0           1 
// CS4                                      0           0           1 
// CS5                                      0           0           1 
// CS6                                      0           0           1 
// CS7                                      0           0           1 

// NCS                                      1           1 

// MPTPR(PTP)                                   H/W design
// Prescaler                               64

Register Configuration Values from Specified Refresh Periods

// Refresh Period                               micro-s     H/W design
// Refresh Period                               micro-s     H/W design
// MAMR(PTA)                                4                         
// MBMR(PTB)                                          156

Actual Refresh Periods from Register Configuration Values

// MAMR(PTA)                                                H/W design
// MBMR(PTB)                                                H/W design
// Acual period                          5.12             micro-s     
// Acual period                                    326.40 micro-s

General Purpose Timers

// GCLK2                             50000000 Hz          
// TINx                             Hz          H/W design

Timer Operated in 16 Bit Mode

// TMRx(ICLK)                                   S/W design
// TMRx(PS)                                     S/W design
// TMRx(FRR)                                    S/W design
// TRRx(reference value)                        S/W design
// TMRx(OM)                                     S/W design

// Timer input frequency              3125000 Hz          
// Timer resolution                      81.9 micro-s     
// Timer reference period               40.96 ms          
// Timer rollover period                40.96 ms          
// TOUTx period                         40.96 ms          
// TOUTx low pulse                       0.32 micro-s

Timer Operated in 32 Bit Mode

// TMRx(ICLK)                                   S/W design
// TMRx(PS)                                     S/W design
// TMRx(FRR)                                    S/W design
// TRRx(reference value)                        S/W design
// TMRx(OM)                                     S/W design

// Timer input frequency               200000 Hz          
// Timer resolution                    1280.0 micro-s     
// Timer reference period            25600.00 s           
// Timer rollover period             25600.00 s           
// TOUTx period                      25600.00 s           
// TOUTx low pulse                       5.00 micro-s

RISC Timers

// GCLK2                             50000000 Hz

Tick period from RCCR(TIMEP) configuration

// RCCR(TIMEP)                                  S/W design
// RISC timers tick period               20.5 micro-s

RCCR(TIMEP) configuration from nominal tick period

// RISC timers nominal tick period  micro-s     S/W design
// RCCR(TIMEP)                             23 
// Actual RISC timers tick period       491.5 micro-s     
// RISC timers range                    32.21 s

Simple Timer Mode

// TM_CMD(period)                               S/W design
// Actual period                        0.614 s

PWM Timer Mode

// TM_CMD(period) even numbered                 S/W design
// TM_CMD(period) odd numbered                  S/W design
// Duty cycle                            20.0 %           
// Approximate PWM resolution               4 bits        
// PWM frequency                      2441.41 Hz

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